One type of dynamic random access memory (DRAM) includes individual memory cells that include a field-effect transistor and a storage capacitor. As the size of integrated circuitry shrinks, the size of the capacitor also shrinks. Generally as the storage capacitor shrinks, the quantity of charge and the time which the charge can be retained decreases as well. Consequently, maintaining an acceptable level of performance of this type of DRAM structure becomes more difficult as the capacitor size decreases. Using capacitor dielectrics having high dielectric constants and increasing capacitor plate surface area through surface roughening, greater vertical dimensions, and other various capacitor shapes have been the conventional approaches to maintaining sufficiently high capacitance.
Another type of DRAM cell uses a structure which is void of a discrete storage capacitor. An example of a capacitor-less DRAM consists essentially of only a single transistor (1T) memory cell. Such DRAM cells use a semiconductor-on-insulator (SOI) structure for storing positive electrical charge in the form of “holes”. The stored positive charge reduces the transistor threshold voltage (Vt), which is the voltage applied to the gate at which the channel region between the pair of source/drain regions becomes conductive. Accordingly, binary data states are represented in a 1T memory cell based on whether the transistor is switched “on” or remains “off” in response to a voltage applied to its gate during a memory read operation.
Various SOI 1T DRAM cell structures have been developed based on metal-oxide-semiconductor (MOS) field-effect transistor (FET) devices using a floating SOI channel body in which the holes accumulate. Accordingly, the source/drain regions are n-type, and the channel region is lightly doped p-type. These types of 1T DRAM cells are generally referred to as floating body cells (FBCs) due to the use of a floating SOI body. As accumulated holes lower the voltage at which the channel becomes conductive, a conductive channel is formed in the same floating SOI body in which the holes accumulate upon appropriate voltage application to the gate of the FET device. A data “1” is written by creating holes (for example, by impact ionization) and push up the body potential to a high level. Conversely, data “0” is written by extracting holes from the body which pulls the body potential down to a low level. By grounding the bit line and by applying negative voltage to the word line, body potential level which is either high or low is held for a certain time. The data can be distinguished using MOSFET current modulated by body potential.
The floating SOI channel body can be designed for use as partially depleted semiconductor-on-insulator (PDSOI) or fully depleted semiconductor-on-insulator (FDSOI), which refers to the extent of the formation of the conductive channel within thickness of the floating SOI body. In the case of FDSOI operation, negative substrate (plate) bias is applied so that the back surface of the semiconductor film accumulates holes. In the case of a partially depleted floating body cell (PDFBC), a neutral volume region exists. Accordingly, the neutral volume region is used in the case of PDFBC, and a bottom “plane” is used in the case of fully depleted floating body cell (FDFBC) for respective hole storage regions representing data states by potential level.
Regardless, writing a “1” to a floating body cell is achieved by voltage application in which excessive holes are stored in the floating body channel region of the FET. Conversely, application of different voltage potentials to the various FET components removes holes of the floating body channel region, thereby writing a “0”. A mostly non-destructive read or data determination state of the FET is conducted typically utilizing a different set of voltage parameters particularly in which the voltage of one of the source/drain regions functioning as a drain is provided at lower voltage than at which such is provided during either a writing “1” operation or a writing “0” operation. There is a need for refresh of a written “1” due to hole loss due to injection into the source/drain because of the forward biased junction. Accordingly, any structure which facilitates quantity of hole storage and minimizes hole loss by any mechanism would be an improvement in the context of floating body field-effect transistors.
Floating body field-effect transistors might also be used in other than DRAM or in other than memory circuitry.